clk: socfpga: clk-pll: Optimize local variables

Since readl() returns a u32, the local variables reg and bypass can also
have the data type u32. Furthermore, divf and divq are derived from reg
and can also be a u32.

Since do_div() casts the divisor to u32 anyway, changing the data type
of divq to u32 removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:

  WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead

Compile-tested only.

Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Thorsten Blum <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>

0 files changed, 0 insertions, 0 deletions