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| author | D Scott Phillips <[email protected]> | 2025-05-13 18:45:14 +0000 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2025-05-19 11:46:26 +0000 |
| commit | fed55f49fad181be9dfb93c06efc4ab2b71a72a9 (patch) | |
| tree | c9059e72c2dccec0c2e34d5198aa74901a1771da /rust/helpers/io.c | |
| parent | KVM: arm64: nv: Remove clearing of ICH_LR<n>.EOI if ICH_LR<n>.HW == 1 (diff) | |
| download | kernel-fed55f49fad181be9dfb93c06efc4ab2b71a72a9.tar.gz kernel-fed55f49fad181be9dfb93c06efc4ab2b71a72a9.zip | |
arm64: errata: Work around AmpereOne's erratum AC04_CPU_23
On AmpereOne AC04, updates to HCR_EL2 can rarely corrupt simultaneous
translations for data addresses initiated by load/store instructions.
Only instruction initiated translations are vulnerable, not translations
from prefetches for example. A DSB before the store to HCR_EL2 is
sufficient to prevent older instructions from hitting the window for
corruption, and an ISB after is sufficient to prevent younger
instructions from hitting the window for corruption.
Signed-off-by: D Scott Phillips <[email protected]>
Reviewed-by: Oliver Upton <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Marc Zyngier <[email protected]>
Diffstat (limited to 'rust/helpers/io.c')
0 files changed, 0 insertions, 0 deletions