clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set

Many qcom clock drivers do not have .width set. In that case value of
(p)->width - 1 will be negative which breaks clock tree. Fix this
by checking if width is zero, and pass 3 to GENMASK if that's the case.

Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
Signed-off-by: Barnabás Czémán <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Christopher Obbard <[email protected]>
Tested-by: Christopher Obbard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

0 files changed, 0 insertions, 0 deletions