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authorGeorge Moussalem <[email protected]>2025-06-13 01:55:07 +0000
committerJakub Kicinski <[email protected]>2025-06-23 18:14:05 +0000
commit82eaf94d69fce20f8859a2b8dae8e7064d9343da (patch)
tree7967d37921eccfb302eb1ede2596944a9b2b877b /net/unix/unix_bpf.c
parenttestptp: add option to enable external timestamping edges (diff)
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dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support
Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018 SoC. Its output pins provide an MDI interface to either an external switch in a PHY to PHY link scenario or is directly attached to an RJ45 connector. The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and 802.3az EEE. For operation, the LDO controller found in the IPQ5018 SoC for which there is provision in the mdio-4019 driver. Two common archictures across IPQ5018 boards are: 1. IPQ5018 PHY --> MDI --> RJ45 connector 2. IPQ5018 PHY --> MDI --> External PHY In a phy to phy architecture, the DAC needs to be configured to accommodate for the short cable length. As such, add an optional boolean property so the driver sets preset DAC register values accordingly. Signed-off-by: George Moussalem <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
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