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| author | Claudiu Beznea <[email protected]> | 2024-12-06 11:13:23 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2024-12-10 11:02:24 +0000 |
| commit | f962745289958e89bf520407728e384e52ea8e27 (patch) | |
| tree | 584a1a0cce0a2ef5b16d3203683cad5fa461ba55 /net/unix/sysctl_net_unix.c | |
| parent | clk: renesas: r8a779h0: Add display clocks (diff) | |
| download | kernel-f962745289958e89bf520407728e384e52ea8e27.tar.gz kernel-f962745289958e89bf520407728e384e52ea8e27.zip | |
clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP
Add clocks, resets and power domains for ADC IP available on the Renesas
RZ/G3S SoC.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'net/unix/sysctl_net_unix.c')
0 files changed, 0 insertions, 0 deletions