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authorClaudiu Beznea <[email protected]>2024-12-10 17:09:31 +0000
committerStephen Boyd <[email protected]>2024-12-10 22:49:27 +0000
commit626b77735a3712b02dabb25be3a0abdde6696bf3 (patch)
treebc0af5c8b683cc9e8b919a27bda6b80a3632fb9b /net/unix/sysctl_net_unix.c
parentclk: versaclock3: Prepare for the addition of 5L35023 device (diff)
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dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator
There are some differences b/w 5L35023 and 5P35023 Versa3 clock generator variants but the same driver could be used with minimal adjustments. The identified differences are PLL2 Fvco, the clock sel bit for SE2 clock and different default values for some registers. Acked-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Biju Das <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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