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| author | Oleksij Rempel <[email protected]> | 2023-10-19 11:14:58 +0000 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2023-10-20 10:50:46 +0000 |
| commit | f600bb612b06adf70ccdefbd3294c71275b650c2 (patch) | |
| tree | 6543d9e6159b923e24429480c3152606fdab1b59 /net/tipc/net.c | |
| parent | Merge branch 'mlxsw-lag-table-allocation' (diff) | |
| download | kernel-f600bb612b06adf70ccdefbd3294c71275b650c2.tar.gz kernel-f600bb612b06adf70ccdefbd3294c71275b650c2.zip | |
net: dsa: microchip: ksz8: Enable MIIM PHY Control reg access
Provide access to MIIM PHY Control register (Reg. 31) through
ksz8_r_phy_ctrl() and ksz8_w_phy_ctrl() functions. Necessary for
upcoming micrel.c patch to address forced link mode configuration.
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Reported-by: kernel test robot <[email protected]>
Signed-off-by: Oleksij Rempel <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'net/tipc/net.c')
0 files changed, 0 insertions, 0 deletions