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| author | Xu Lu <[email protected]> | 2025-01-03 09:32:19 +0000 |
|---|---|---|
| committer | Joerg Roedel <[email protected]> | 2025-01-06 11:37:19 +0000 |
| commit | 8d8d3752c0a4f7fb072352837cbdbf57c02df239 (patch) | |
| tree | aeb2f10f1b12dc6ff9782713ab906f55da9e4975 /net/switchdev/switchdev.c | |
| parent | iommu/riscv: Add support for platform msi (diff) | |
| download | kernel-8d8d3752c0a4f7fb072352837cbdbf57c02df239.tar.gz kernel-8d8d3752c0a4f7fb072352837cbdbf57c02df239.zip | |
iommu/riscv: Empty iommu queue before enabling it
Changing cqen/fqen/pqen from 0 to 1 sets the cqh/fqt/pqt registers to 0.
But the cqt/fqh/pqh registers are left unmodified. This commit resets
cqt/fqh/pqh registers to ensure corresponding queues are empty before
being enabled during initialization.
Signed-off-by: Xu Lu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Joerg Roedel <[email protected]>
Diffstat (limited to 'net/switchdev/switchdev.c')
0 files changed, 0 insertions, 0 deletions