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| author | Stafford Horne <[email protected]> | 2025-01-14 17:07:21 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2025-02-14 21:06:36 +0000 |
| commit | 713e788c0e07e185fd44dd581f74855ef149722f (patch) | |
| tree | ed994ab5a620e5840df8c2b9a8f2e70f67b9d87c /net/switchdev/switchdev.c | |
| parent | riscv/futex: sign extend compare value in atomic cmpxchg (diff) | |
| download | kernel-713e788c0e07e185fd44dd581f74855ef149722f.tar.gz kernel-713e788c0e07e185fd44dd581f74855ef149722f.zip | |
rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
When working on OpenRISC support for restartable sequences I noticed
and fixed these two issues with the riscv support bits.
1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
passed to the macro. Fix this by adding 'inc' to the list of macro
arguments.
2 The inline asm input constraints for 'inc' and 'off' use "er", The
riscv gcc port does not have an "e" constraint, this looks to be
copied from the x86 port. Fix this by just using an "r" constraint.
I have compile tested this only for riscv. However, the same fixes I
use in the OpenRISC rseq selftests and everything passes with no issues.
Fixes: 171586a6ab66 ("selftests/rseq: riscv: Template memory ordering and percpu access mode")
Signed-off-by: Stafford Horne <[email protected]>
Tested-by: Charlie Jenkins <[email protected]>
Reviewed-by: Charlie Jenkins <[email protected]>
Reviewed-by: Mathieu Desnoyers <[email protected]>
Acked-by: Shuah Khan <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'net/switchdev/switchdev.c')
0 files changed, 0 insertions, 0 deletions
