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| author | Florian Fainelli <[email protected]> | 2019-05-13 20:25:22 +0000 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <[email protected]> | 2019-05-15 19:36:49 +0000 |
| commit | 7025fdbea3a67c5980b94574b755a5fd65ea8a36 (patch) | |
| tree | a2a8eb2c2fd6d9c0bc6370cf392989f733ecd588 /lib/timerqueue.c | |
| parent | perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events (diff) | |
| download | kernel-7025fdbea3a67c5980b94574b755a5fd65ea8a36.tar.gz kernel-7025fdbea3a67c5980b94574b755a5fd65ea8a36.zip | |
perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
up to the RC_ST_SPEC (0x91) event with the exception of:
- L1D_CACHE_REFILL_INNER (0x44)
- L1D_CACHE_REFILL_OUTER (0x45)
- L1D_TLB_RD (0x4E)
- L1D_TLB_WR (0x4F)
- L2D_TLB_REFILL_RD (0x5C)
- L2D_TLB_REFILL_WR (0x5D)
- L2D_TLB_RD (0x5E)
- L2D_TLB_WR (0x5F)
- STREX_SPEC (0x6F)
Create an appropriate JSON file for mapping those events and update the
mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
file.
Signed-off-by: Florian Fainelli <[email protected]>
Reviewed-by: John Garry <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Catalin Marinas <[email protected]>
Cc: Ganapatrao Kulkarni <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Namhyung Kim <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Sean V Kelley <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: [email protected] (moderated list:arm pmu profiling and debugging)
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
Diffstat (limited to 'lib/timerqueue.c')
0 files changed, 0 insertions, 0 deletions