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authorAnkit Agrawal <[email protected]>2025-01-24 18:31:00 +0000
committerAlex Williamson <[email protected]>2025-01-27 16:43:33 +0000
commit6a9eb2d125ba90d13b45bcfabcddf9f61268f6a8 (patch)
treed46e750c7658cb8e75c284d6f5841a9bfd04a6b3 /lib/timerqueue.c
parentvfio/nvgrace-gpu: Read dvsec register to determine need for uncached resmem (diff)
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vfio/nvgrace-gpu: Expose the blackwell device PF BAR1 to the VM
There is a HW defect on Grace Hopper (GH) to support the Multi-Instance GPU (MIG) feature [1] that necessiated the presence of a 1G region carved out from the device memory and mapped as uncached. The 1G region is shown as a fake BAR (comprising region 2 and 3) to workaround the issue. The Grace Blackwell systems (GB) differ from GH systems in the following aspects: 1. The aforementioned HW defect is fixed on GB systems. 2. There is a usable BAR1 (region 2 and 3) on GB systems for the GPUdirect RDMA feature [2]. This patch accommodate those GB changes by showing the 64b physical device BAR1 (region2 and 3) to the VM instead of the fake one. This takes care of both the differences. Moreover, the entire device memory is exposed on GB as cacheable to the VM as there is no carveout required. Link: https://www.nvidia.com/en-in/technologies/multi-instance-gpu/ [1] Link: https://docs.nvidia.com/cuda/gpudirect-rdma/ [2] Cc: Kevin Tian <[email protected]> CC: Jason Gunthorpe <[email protected]> Suggested-by: Alex Williamson <[email protected]> Signed-off-by: Ankit Agrawal <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alex Williamson <[email protected]>
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