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| author | Douglas Anderson <[email protected]> | 2023-06-16 15:14:38 +0000 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-06-22 19:20:12 +0000 |
| commit | c0877829ada0406233aee5bd54f6813db79d5f1f (patch) | |
| tree | 6ef955ec774e10b992c07b72aeec71eb63e06e5f /lib/test_vmalloc.c | |
| parent | arm64: dts: qcom: sm8550: Use the correct LLCC register scheme (diff) | |
| download | kernel-c0877829ada0406233aee5bd54f6813db79d5f1f.tar.gz kernel-c0877829ada0406233aee5bd54f6813db79d5f1f.zip | |
dt-bindings: firmware: qcom,scm: Document that SCM can be dma-coherent
Trogdor devices use firmware backed by TF-A instead of Qualcomm's
normal TZ. On TF-A we end up mapping memory as cacheable. Specifically,
you can see in Trogdor's TF-A code [1] in qti_sip_mem_assign() that we
call qti_mmap_add_dynamic_region() with MT_RO_DATA. This translates
down to MT_MEMORY instead of MT_NON_CACHEABLE or MT_DEVICE.
Let's allow devices like trogdor to be described properly by allowing
"dma-coherent" in the SCM node.
Signed-off-by: Douglas Anderson <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/20230616081440.v2.1.Ie79b5f0ed45739695c9970df121e11d724909157@changeid
Signed-off-by: Bjorn Andersson <[email protected]>
Diffstat (limited to 'lib/test_vmalloc.c')
0 files changed, 0 insertions, 0 deletions