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| author | Imre Deak <[email protected]> | 2025-06-05 08:28:46 +0000 |
|---|---|---|
| committer | Joonas Lahtinen <[email protected]> | 2025-06-23 12:53:42 +0000 |
| commit | a3ef3c2da675a8a564c8bea1a511cdd0a2a9aa49 (patch) | |
| tree | 795285f59b21d63a5761ec8373960113181931e8 /lib/crypto/mpi/mpi-cmp.c | |
| parent | drm/i915/snps_hdmi_pll: Fix 64-bit divisor truncation by using div64_u64 (diff) | |
| download | kernel-a3ef3c2da675a8a564c8bea1a511cdd0a2a9aa49.tar.gz kernel-a3ef3c2da675a8a564c8bea1a511cdd0a2a9aa49.zip | |
drm/dp: Change AUX DPCD probe address from DPCD_REV to LANE0_1_STATUS
Reading DPCD registers has side-effects in general. In particular
accessing registers outside of the link training register range
(0x102-0x106, 0x202-0x207, 0x200c-0x200f, 0x2216) is explicitly
forbidden by the DP v2.1 Standard, see
3.6.5.1 DPTX AUX Transaction Handling Mandates
3.6.7.4 128b/132b DP Link Layer LTTPR Link Training Mandates
Based on my tests, accessing the DPCD_REV register during the link
training of an UHBR TBT DP tunnel sink leads to link training failures.
Solve the above by using the DP_LANE0_1_STATUS (0x202) register for the
DPCD register access quirk.
Cc: <[email protected]>
Cc: Ville Syrjälä <[email protected]>
Cc: Jani Nikula <[email protected]>
Acked-by: Jani Nikula <[email protected]>
Signed-off-by: Imre Deak <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
(cherry picked from commit a40c5d727b8111b5db424a1e43e14a1dcce1e77f)
Signed-off-by: Joonas Lahtinen <[email protected]>
Diffstat (limited to 'lib/crypto/mpi/mpi-cmp.c')
0 files changed, 0 insertions, 0 deletions