diff options
| author | Geert Uytterhoeven <[email protected]> | 2018-05-23 09:02:04 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2018-05-24 14:15:39 +0000 |
| commit | 0921e11e1e12802ae0a3c19cb02e33354ca51967 (patch) | |
| tree | 0532b6b2e20aa022f1341675d8fcc268e06bb7a5 /fs/proc/namespaces.c | |
| parent | spi: bcm2835aux: ensure interrupts are enabled for shared handler (diff) | |
| download | kernel-0921e11e1e12802ae0a3c19cb02e33354ca51967.tar.gz kernel-0921e11e1e12802ae0a3c19cb02e33354ca51967.zip | |
spi: sh-msiof: Fix setting SIRMDR1.SYNCAC to match SITMDR1.SYNCAC
According to section 59.2.4 MSIOF Receive Mode Register 1 (SIRMDR1) in
the R-Car Gen3 datasheet Rev.1.00, the value of the SIRMDR1.SYNCAC bit
must match the value of the SITMDR1.SYNCAC bit. However,
sh_msiof_spi_setup() changes only the latter.
Fix this by updating the SIRMDR1 register like the SITMDR1 register,
taking into account register bits that exist in SITMDR1 only.
Reported-by: Renesas BSP team via Yoshihiro Shimoda <[email protected]>
Fixes: 7ff0b53c4051145d ("spi: sh-msiof: Avoid writing to registers from spi_master.setup()")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'fs/proc/namespaces.c')
0 files changed, 0 insertions, 0 deletions