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| author | Valentin Caron <[email protected]> | 2023-09-06 13:27:35 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2023-09-11 00:24:00 +0000 |
| commit | 6de8a70c84ee0586fdde4e671626b9caca6aed74 (patch) | |
| tree | 483995488b72c8d00f42b51f5a2266bbe9a603d6 /fs/jbd2/commit.c | |
| parent | spi: nxp-fspi: reset the FLSHxCR1 registers (diff) | |
| download | kernel-6de8a70c84ee0586fdde4e671626b9caca6aed74.tar.gz kernel-6de8a70c84ee0586fdde4e671626b9caca6aed74.zip | |
spi: stm32: add a delay before SPI disable
As explained in errata sheet, in section "2.14.5 Truncation of SPI output
signals after EOT event":
On STM32MP1x, EOT interrupt can be thrown before the true end of
communication.
So we add a delay of a half period to wait the real end of the
transmission.
Link: https://www.st.com/resource/en/errata_sheet/es0539-stm32mp131x3x5x-device-errata-stmicroelectronics.pdf
Signed-off-by: Valentin Caron <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'fs/jbd2/commit.c')
0 files changed, 0 insertions, 0 deletions