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| author | Benjamin Herrenschmidt <[email protected]> | 2018-01-12 05:48:01 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2018-01-27 00:22:48 +0000 |
| commit | 6671507f0fbd582b4003f837ab791d03ade8e0f4 (patch) | |
| tree | 87615147b69008ac30cfcff53765d749fc73e979 /fs/jbd2/commit.c | |
| parent | clk: aspeed: Fix return value check in aspeed_cc_init() (diff) | |
| download | kernel-6671507f0fbd582b4003f837ab791d03ade8e0f4.tar.gz kernel-6671507f0fbd582b4003f837ab791d03ade8e0f4.zip | |
clk: aspeed: Handle inverse polarity of USB port 1 clock gate
The USB port 1 clock gate control has an inversed polarity
from all the other clock gates in the chip. This makes the
aspeed_clk_{enable,disable} functions honor the flag
CLK_GATE_SET_TO_DISABLE and set that flag appropriately
so it's set for all clocks except USB port 1.
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'fs/jbd2/commit.c')
0 files changed, 0 insertions, 0 deletions