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| author | Lorenzo Pieralisi <[email protected]> | 2023-10-06 12:59:25 +0000 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2023-10-07 11:47:12 +0000 |
| commit | 5e5c636c69bdba04033161bbb111fbb6f1f6661e (patch) | |
| tree | fa77601ec8420789b2ff94fb65f817e03b031e24 /fs/jbd2/commit.c | |
| parent | dt-bindings: interrupt-controller: renesas,irqc: Add r8a779f0 support (diff) | |
| download | kernel-5e5c636c69bdba04033161bbb111fbb6f1f6661e.tar.gz kernel-5e5c636c69bdba04033161bbb111fbb6f1f6661e.zip | |
dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property
The GIC v3 specifications allow redistributors and ITSes interconnect
ports used to access memory to be wired up in a way that makes the
respective initiators/memory observers non-coherent.
Add the standard dma-noncoherent property to the GICv3 bindings to
allow firmware to describe the redistributors/ITSes components and
interconnect ports behaviour in system designs where the redistributors
and ITSes are not coherent with the CPU.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Rob Herring <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'fs/jbd2/commit.c')
0 files changed, 0 insertions, 0 deletions
