clk: qcom: Add A53 PLL support

The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,
a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources
are connected to a mux and half-integer divider, which is feeding the
CPU cores.

This patch adds support for the primary CPU PLL which generates the
higher range of frequencies above 1GHz.

Signed-off-by: Georgi Djakov <[email protected]>
Acked-by: Bjorn Andersson <[email protected]>
Tested-by: Amit Kucheria <[email protected]>
[[email protected]: Move to devm provider registration,
NUL terminate frequency table, made tristate/modular]
Signed-off-by: Stephen Boyd <[email protected]>

0 files changed, 0 insertions, 0 deletions