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authorKrishna Kurapati <[email protected]>2024-11-12 18:20:18 +0000
committerGreg Kroah-Hartman <[email protected]>2024-11-13 06:13:09 +0000
commitce25e2a8d82de7f8bcbedd18973e5b8030749d45 (patch)
treedbb3900c19b63d28b267ee5dbd35660793782774 /drivers/usb/cdns3
parentusb: dwc3: gadget: Add missing check for single port RAM in TxFIFO resizing l... (diff)
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usb: dwc3: core: Set force_gen1 bit for all applicable SuperSpeed ports
Currently if the maximum-speed is set to Super Speed for a 3.1 Gen2 capable controller, the FORCE_GEN1 bit of LLUCTL register is set only for one SuperSpeed port (or the first port) present. Modify the logic to set the FORCE_GEN1 bit for all ports if speed is being limited to Gen-1. Suggested-by: Thinh Nguyen <[email protected]> Signed-off-by: Krishna Kurapati <[email protected]> Acked-by: Thinh Nguyen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'drivers/usb/cdns3')
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