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| author | Stephane Eranian <[email protected]> | 2022-08-18 05:46:13 +0000 |
|---|---|---|
| committer | Peter Zijlstra <[email protected]> | 2022-08-19 17:47:31 +0000 |
| commit | d4bdb0bebc5ba3299d74f123c782d99cd4e25c49 (patch) | |
| tree | b008b58262d83658571f1d51838c019e501324dc /drivers/usb/cdns3/cdns3-imx.c | |
| parent | perf/x86/core: Set pebs_capable and PMU_FL_PEBS_ALL for the Baseline (diff) | |
| download | kernel-d4bdb0bebc5ba3299d74f123c782d99cd4e25c49.tar.gz kernel-d4bdb0bebc5ba3299d74f123c782d99cd4e25c49.zip | |
perf/x86/intel/ds: Fix precise store latency handling
With the existing code in store_latency_data(), the memory operation (mem_op)
returned to the user is always OP_LOAD where in fact, it should be OP_STORE.
This comes from the fact that the function is simply grabbing the information
from a data source map which covers only load accesses. Intel 12th gen CPU
offers precise store sampling that captures both the data source and latency.
Therefore it can use the data source mapping table but must override the
memory operation to reflect stores instead of loads.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Stephane Eranian <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/usb/cdns3/cdns3-imx.c')
0 files changed, 0 insertions, 0 deletions