diff options
| author | Steve Wilkins <[email protected]> | 2024-07-15 11:13:56 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2024-07-15 18:08:19 +0000 |
| commit | 9cf71eb0faef4bff01df4264841b8465382d7927 (patch) | |
| tree | 3aa695bdfede52d66d8f9b07854b4c5a2da0987e /drivers/spi/spi-microchip-core.c | |
| parent | spi: microchip-core: fix init function not setting the master and motorola modes (diff) | |
| download | kernel-9cf71eb0faef4bff01df4264841b8465382d7927.tar.gz kernel-9cf71eb0faef4bff01df4264841b8465382d7927.zip | |
spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
While transmitting with rx_len == 0, the RX FIFO is not going to be
emptied in the interrupt handler. A subsequent transfer could then
read crap from the previous transfer out of the RX FIFO into the
start RX buffer. The core provides a register that will empty the RX and
TX FIFOs, so do that before each transfer.
Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers")
Signed-off-by: Steve Wilkins <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Link: https://patch.msgid.link/20240715-flammable-provoke-459226d08e70@wendy
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'drivers/spi/spi-microchip-core.c')
| -rw-r--r-- | drivers/spi/spi-microchip-core.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index aa72b9dd8956..057092506bd5 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -91,6 +91,8 @@ #define REG_CONTROL2 (0x28) #define REG_COMMAND (0x2c) #define COMMAND_CLRFRAMECNT BIT(4) +#define COMMAND_TXFIFORST BIT(3) +#define COMMAND_RXFIFORST BIT(2) #define REG_PKTSIZE (0x30) #define REG_CMD_SIZE (0x34) #define REG_HWSTATUS (0x38) @@ -496,6 +498,8 @@ static int mchp_corespi_transfer_one(struct spi_controller *host, mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH) ? FIFO_DEPTH : spi->tx_len); + mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST); + mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select); while (spi->tx_len) |