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authorHans de Goede <[email protected]>2017-08-29 12:08:35 +0000
committerWolfram Sang <[email protected]>2017-08-31 18:27:39 +0000
commit231d069fcde22bd0582c2c9564f1b334d280c7d7 (patch)
tree8f14e8489cf675c64a2f193ebaea0392b1e3d9c1 /drivers/pwm/pwm-twl.c
parenti2c: ismt: Return EMSGSIZE for block reads with bogus length (diff)
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i2c: designware: Round down ACPI provided clk to nearest supported clk
The Lenovo Miix2 8 DSDT contains an i2c clk / bus speed of 1700000 Hz for one if its devices, which is not supported. This is the second DSDT to show up with an unsupported clk in a short time, remove the hardcoded fix for DSDTs with a 1 MiHz clock and simply always round down the clk to the nearest supported value. Reported-by: [email protected] Fixes: 682c6c2188 ("i2c: designware: Some broken DSTDs use 1MiHz ...") Signed-off-by: Hans de Goede <[email protected]> Acked-by: Jarkko Nikula <[email protected]> Signed-off-by: Wolfram Sang <[email protected]>
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