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authorFabrice Gasnier <[email protected]>2025-04-29 12:51:28 +0000
committerLee Jones <[email protected]>2025-05-13 10:12:52 +0000
commit4f8ceb0302b36c5f78bcc8d0e7cfa2372fba134c (patch)
tree2af1bfabaee9a2ebba3c859ddbacd771c966d259 /drivers/pwm/pwm-stm32-lp.c
parentdt-bindings: mfd: stm32-lptimer: Add support for stm32mp25 (diff)
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mfd: stm32-lptimer: Add support for stm32mp25
Add support for STM32MP25 SoC. A new hardware configuration register (HWCFGR2) has been added, to gather number of capture/compare channels, autonomous mode and input capture capability. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features. This can now be read from HWCFGR registers. Add new registers to the stm32-lptimer.h: CCMR1, CCR2, HWCFGR1/2 and VERR. Update the stm32_lptimer data struct so signal the number of capture/compare channels to the child devices. Also Remove some unused bit masks (CMPOK_ARROK / CMPOKCF_ARROKCF). Signed-off-by: Fabrice Gasnier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lee Jones <[email protected]>
Diffstat (limited to 'drivers/pwm/pwm-stm32-lp.c')
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