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| author | [email protected] <[email protected]> | 2018-06-08 19:22:35 +0000 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2018-07-09 17:06:21 +0000 |
| commit | db6c51ab156a2ec29edff41b1ebc1fe7d04a9614 (patch) | |
| tree | 9ead980e09f479c2cdf72135d3d4bd85f80af7c8 /drivers/pwm/pwm-omap-dmtimer.c | |
| parent | pwm: fsl-ftm: Added a dedicated IP interface clock (diff) | |
| download | kernel-db6c51ab156a2ec29edff41b1ebc1fe7d04a9614.tar.gz kernel-db6c51ab156a2ec29edff41b1ebc1fe7d04a9614.zip | |
pwm: fsl-ftm: Added the support of per-compatible data
On the i.MX8x SoC family, an additional PWM enable bit is added for each
PWM channel in the register FTM_SC[23:16]. It supports 8 channels. Bit
16 is for channel 0, and bit 23 is for channel 7. As the IP version
information can not be obtained via any of the FTM registers, a property
of "has_enable_bits" is added via per-compatible data structure.
Signed-off-by: Shenwei Wang <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'drivers/pwm/pwm-omap-dmtimer.c')
0 files changed, 0 insertions, 0 deletions