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| author | Uwe Kleine-König <[email protected]> | 2025-07-28 16:00:18 +0000 |
|---|---|---|
| committer | Uwe Kleine-König <[email protected]> | 2025-07-29 15:46:29 +0000 |
| commit | f21d136caf8171f94159d975ea4620c164431bd9 (patch) | |
| tree | 3943d3b87d044c7ae6c49927cc1a61e8130cf652 /drivers/pwm/pwm-imx-tpm.c | |
| parent | pwm: mediatek: Handle hardware enable and clock enable separately (diff) | |
| download | kernel-f21d136caf8171f94159d975ea4620c164431bd9.tar.gz kernel-f21d136caf8171f94159d975ea4620c164431bd9.zip | |
pwm: mediatek: Fix duty and period setting
The period generated by the hardware is
(PWMDWIDTH + 1) << CLKDIV) / freq
according to my tests with a signal analyser and also the documentation.
The current algorithm doesn't consider the `+ 1` part and so configures
slightly too high periods. The same issue exists for the duty cycle
setting. So subtract 1 from both the register values for period and
duty cycle. If period is 0, bail out, if duty_cycle is 0, just disable
the PWM which results in a constant low output.
Fixes: caf065f8fd58 ("pwm: Add MediaTek PWM support")
Signed-off-by: Uwe Kleine-König <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/6d1fa87a76f8020bfe3171529b8e19baffceab10.1753717973.git.u.kleine-koenig@baylibre.com
Cc: [email protected]
Signed-off-by: Uwe Kleine-König <[email protected]>
Diffstat (limited to 'drivers/pwm/pwm-imx-tpm.c')
0 files changed, 0 insertions, 0 deletions