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| author | Ben Zong-You Xie <[email protected]> | 2025-07-11 13:30:21 +0000 |
|---|---|---|
| committer | Arnd Bergmann <[email protected]> | 2025-07-21 14:51:52 +0000 |
| commit | 65bbf10b934ae17e1ce7a673355723eb806668ac (patch) | |
| tree | a7ca32027a179b9b767e52528158e072019b496a /drivers/platform/x86/intel/pmt/class.c | |
| parent | dt-bindings: interrupt-controller: add Andes machine-level software interrupt... (diff) | |
| download | kernel-65bbf10b934ae17e1ce7a673355723eb806668ac.tar.gz kernel-65bbf10b934ae17e1ce7a673355723eb806668ac.zip | |
dt-bindings: timer: add Andes machine timer
Add the DT binding documentation for Andes machine timer.
The RISC-V architecture defines a machine timer that provides a real-time
counter and generates timer interrupts. Andes machiner timer (PLMT0) is
the implementation of the machine timer, and it contains memory-mapped
registers (mtime and mtimecmp). This device supports up to 32 cores.
Acked-by: Conor Dooley <[email protected]>
Signed-off-by: Ben Zong-You Xie <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
Diffstat (limited to 'drivers/platform/x86/intel/pmt/class.c')
0 files changed, 0 insertions, 0 deletions