diff options
| author | Srinivas Pandruvada <[email protected]> | 2023-03-08 07:06:37 +0000 |
|---|---|---|
| committer | Hans de Goede <[email protected]> | 2023-03-16 14:18:02 +0000 |
| commit | 0ab147bb840fca2bc3bca88f320b34c5b5cc013c (patch) | |
| tree | d241f5ff16cbe9f2a5cc3fb10c94dc92f46f8a7c /drivers/platform/x86/intel/pmt/class.c | |
| parent | platform/x86: ISST: Enumerate TPMI SST and create framework (diff) | |
| download | kernel-0ab147bb840fca2bc3bca88f320b34c5b5cc013c.tar.gz kernel-0ab147bb840fca2bc3bca88f320b34c5b5cc013c.zip | |
platform/x86: ISST: Parse SST MMIO and update instance
SST registers are presented to OS in multi-layer structures starting
with a SST header showing version information freezing current
definition.
For details on SST terminology refer to
Documentation/admin-guide/pm/intel-speed-select.rst
under the kernel documentation
SST TPMI details are published in the following document:
https://github.com/intel/tpmi_power_management/blob/main/SST_TPMI_public_disclosure_FINAL.docx
SST MMIO structure layout follows:
SST-HEADER
SST-CP Header
SST-CP CONTROL
SST-CP STATUS
SST-CP CONFIG0
SST-CP CONFIG1
...
...
SST-PP Header
SST-PP OFFSET_0
SST-PP OFFSET_1
SST_PP_0_INFO
SST_PP_1_INFO
SST_PP_2_INFO
SST_PP_3_INFO
SST-PP CONTROL
SST-PP STATUS
Each register bank contains information to get to next lower level
information. This information is parsed and stored in the struct
tpmi_per_power_domain_info for each domain. This information is
used to process each SST requests.
Signed-off-by: Srinivas Pandruvada <[email protected]>
Reviewed-by: Zhang Rui <[email protected]>
Tested-by: Pragya Tanwar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Hans de Goede <[email protected]>
Diffstat (limited to 'drivers/platform/x86/intel/pmt/class.c')
0 files changed, 0 insertions, 0 deletions