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authorHans de Goede <[email protected]>2023-01-27 20:37:29 +0000
committerHans de Goede <[email protected]>2023-02-03 09:22:35 +0000
commit7a88de319c8ef9a971e8b1c4004512e39b7680f2 (patch)
treec6669956cf478b94291b9a9c87d48f4cae2fe433 /drivers/platform/x86/intel/int3472/discrete.c
parentplatform/x86: int3472/discrete: Move GPIO request to skl_int3472_register_clo... (diff)
downloadkernel-7a88de319c8ef9a971e8b1c4004512e39b7680f2.tar.gz
kernel-7a88de319c8ef9a971e8b1c4004512e39b7680f2.zip
platform/x86: int3472/discrete: Get the polarity from the _DSM entry
According to: https://github.com/intel/ipu6-drivers/blob/master/patch/int3472-support-independent-clock-and-LED-gpios-5.17%2B.patch Bits 31-24 of the _DSM pin entry integer value codes the active-value, that is the actual physical signal (0 or 1) which needs to be output on the pin to turn the sensor chip on (to make it active). So if bits 31-24 are 0 for a reset pin, then the actual value of the reset pin needs to be 0 to take the chip out of reset. IOW in this case the reset signal is active-high rather then the default active-low. And if bits 31-24 are 0 for a clk-en pin then the actual value of the clk pin needs to be 0 to enable the clk. So in this case the clk-en signal is active-low rather then the default active-high. IOW if bits 31-24 are 0 for a pin, then the default polarity of the pin is inverted. Add a check for this and also propagate this new polarity to the clock registration. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Sakari Ailus <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/platform/x86/intel/int3472/discrete.c')
-rw-r--r--drivers/platform/x86/intel/int3472/discrete.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/platform/x86/intel/int3472/discrete.c b/drivers/platform/x86/intel/int3472/discrete.c
index b7752c2b798d..96963e30ab6c 100644
--- a/drivers/platform/x86/intel/int3472/discrete.c
+++ b/drivers/platform/x86/intel/int3472/discrete.c
@@ -220,11 +220,11 @@ static int skl_int3472_handle_gpio_resources(struct acpi_resource *ares,
struct int3472_discrete_device *int3472 = data;
struct acpi_resource_gpio *agpio;
union acpi_object *obj;
+ u8 active_value, type;
const char *err_msg;
const char *func;
u32 polarity;
int ret;
- u8 type;
if (!acpi_gpio_get_io_resource(ares, &agpio))
return 1;
@@ -248,6 +248,15 @@ static int skl_int3472_handle_gpio_resources(struct acpi_resource *ares,
int3472_get_func_and_polarity(type, &func, &polarity);
+ /* If bits 31-24 of the _DSM entry are all 0 then the signal is inverted */
+ active_value = obj->integer.value >> 24;
+ if (!active_value)
+ polarity ^= GPIO_ACTIVE_LOW;
+
+ dev_dbg(int3472->dev, "%s %s pin %d active-%s\n", func,
+ agpio->resource_source.string_ptr, agpio->pin_table[0],
+ (polarity == GPIO_ACTIVE_HIGH) ? "high" : "low");
+
switch (type) {
case INT3472_GPIO_TYPE_RESET:
case INT3472_GPIO_TYPE_POWERDOWN:
@@ -257,7 +266,7 @@ static int skl_int3472_handle_gpio_resources(struct acpi_resource *ares,
break;
case INT3472_GPIO_TYPE_CLK_ENABLE:
- ret = skl_int3472_register_clock(int3472, agpio);
+ ret = skl_int3472_register_clock(int3472, agpio, polarity);
if (ret)
err_msg = "Failed to register clock\n";