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| author | Krishna Chaitanya Chundru <[email protected]> | 2025-03-28 10:28:30 +0000 |
|---|---|---|
| committer | Manivannan Sadhasivam <[email protected]> | 2025-04-19 14:12:33 +0000 |
| commit | 57a4591df70900252265ecfd6eeba95ce2021504 (patch) | |
| tree | ecc79288586f6439cd336f6757f67644268dcc05 /drivers/pci/controller/dwc | |
| parent | Linux 6.15-rc1 (diff) | |
| download | kernel-57a4591df70900252265ecfd6eeba95ce2021504.tar.gz kernel-57a4591df70900252265ecfd6eeba95ce2021504.zip | |
PCI: of: Add of_pci_get_equalization_presets() API
PCIe equalization presets are predefined settings used to optimize
signal integrity by compensating for signal loss and distortion in
high-speed data transmission.
As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates
of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to
configure lane equalization presets for each lane to enhance the PCIe
link reliability. Each preset value represents a different combination
of pre-shoot and de-emphasis values. For each data rate, different
registers are defined: for 8.0 GT/s, registers are defined in section
7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has
an extra receiver preset hint, requiring 16 bits per lane, while the
remaining data rates use 8 bits per lane.
Based on the number of lanes and the supported data rate,
of_pci_get_equalization_presets() reads the device tree property and
stores in the presets structure.
Signed-off-by: Krishna Chaitanya Chundru <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Link: https://patch.msgid.link/[email protected]
Diffstat (limited to 'drivers/pci/controller/dwc')
0 files changed, 0 insertions, 0 deletions
