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| author | Jim Quinlan <[email protected]> | 2024-08-15 22:57:20 +0000 |
|---|---|---|
| committer | Krzysztof Wilczyński <[email protected]> | 2024-09-04 13:59:28 +0000 |
| commit | 30eb2080fe2043c3e61c1ae4bb6917800b10fb08 (patch) | |
| tree | eaf63abfeacdc9d2410c11e65dba494e5bfa2f55 /drivers/pci/controller/dwc | |
| parent | PCI: brcmstb: Use swinit reset if available (diff) | |
| download | kernel-30eb2080fe2043c3e61c1ae4bb6917800b10fb08.tar.gz kernel-30eb2080fe2043c3e61c1ae4bb6917800b10fb08.zip | |
PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific
Do preparatory work for the 7712 SoC, which is introduced in a
future commit.
Our HW design has changed two register offsets for the 7712, where
previously it was a common value for all Broadcom SoCs with PCIe
cores.
Specifically, the two offsets are to the registers HARD_DEBUG and
INTR2_CPU_BASE.
Link: https://lore.kernel.org/linux-pci/[email protected]
Signed-off-by: Jim Quinlan <[email protected]>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Tested-by: Florian Fainelli <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Stanimir Varbanov <[email protected]>
Diffstat (limited to 'drivers/pci/controller/dwc')
0 files changed, 0 insertions, 0 deletions
