diff options
| author | Shashank Babu Chinta Venkata <[email protected]> | 2024-09-11 15:26:29 +0000 |
|---|---|---|
| committer | Krzysztof Wilczyński <[email protected]> | 2024-09-13 14:44:59 +0000 |
| commit | d14bc28af34fb8b599c1cc4ce24a2833e60ade8f (patch) | |
| tree | 78543645ae3f551c8e39fad8b9ea9e74fc67947b /drivers/pci/controller/dwc/pcie-qcom-common.c | |
| parent | PCI: qcom: Add equalization settings for 16.0 GT/s (diff) | |
| download | kernel-d14bc28af34fb8b599c1cc4ce24a2833e60ade8f.tar.gz kernel-d14bc28af34fb8b599c1cc4ce24a2833e60ade8f.zip | |
PCI: qcom: Add RX lane margining settings for 16.0 GT/s
Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate.
These settings improve link stability while operating at high date
rates and helps to improve signal quality.
Link: https://lore.kernel.org/linux-pci/[email protected]
Tested-by: Johan Hovold <[email protected]>
Signed-off-by: Shashank Babu Chinta Venkata <[email protected]>
[mani: dropped the code refactoring and minor changes]
Signed-off-by: Manivannan Sadhasivam <[email protected]>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-qcom-common.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-qcom-common.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c index 596a35449de1..3aad19b56da8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.c +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c @@ -45,3 +45,34 @@ void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); } EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); + +void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) +{ + u32 reg; + + reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF); + reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET | + MARGINING_NUM_VOLTAGE_STEPS | + MARGINING_MAX_TIMING_OFFSET | + MARGINING_NUM_TIMING_STEPS); + reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) | + FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) | + FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) | + FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10); + dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg); + + reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF); + reg |= MARGINING_IND_ERROR_SAMPLER | + MARGINING_SAMPLE_REPORTING_METHOD | + MARGINING_IND_LEFT_RIGHT_TIMING | + MARGINING_VOLTAGE_SUPPORTED; + reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE | + MARGINING_MAXLANES | + MARGINING_SAMPLE_RATE_TIMING | + MARGINING_SAMPLE_RATE_VOLTAGE); + reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) | + FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) | + FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f); + dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg); +} +EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining); |