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| author | Krishna Chaitanya Chundru <[email protected]> | 2025-03-28 10:28:31 +0000 |
|---|---|---|
| committer | Manivannan Sadhasivam <[email protected]> | 2025-04-19 14:12:38 +0000 |
| commit | f9eb654fb194e7c404d4984481a18edb9b1c1d7c (patch) | |
| tree | a2f5ffc52d4e4bef818b128a7097311d05b7c2bc /drivers/pci/controller/dwc/pcie-designware.c | |
| parent | PCI: of: Add of_pci_get_equalization_presets() API (diff) | |
| download | kernel-f9eb654fb194e7c404d4984481a18edb9b1c1d7c.tar.gz kernel-f9eb654fb194e7c404d4984481a18edb9b1c1d7c.zip | |
PCI: dwc: Update pci->num_lanes to maximum supported link width
If the num-lanes property is not present in the devicetree, update
pci->num_lanes with the hardware supported maximum link width using
the newly introduced dw_pcie_link_get_max_link_width() API.
The API is used to get the Maximum Link Width (MLW) of the controller.
Signed-off-by: Krishna Chaitanya Chundru <[email protected]>
[mani: reworded commit message a bit]
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Link: https://patch.msgid.link/[email protected]
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 97d76d3dc066..cafe91bd9c34 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -781,6 +781,14 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) } +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +{ + u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) { u32 lnkcap, lwsc, plc; |