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| author | saturneric <[email protected]> | 2025-10-16 21:50:56 +0000 |
|---|---|---|
| committer | saturneric <[email protected]> | 2025-10-16 21:50:56 +0000 |
| commit | 5293dcd7ffda472dbf326c81877bb63d2bfcbd10 (patch) | |
| tree | da3be05c4aa1646e5f26a84cd75d83fe866c5358 /drivers/pci/controller/dwc/pcie-designware.c | |
| parent | Merge tag 'v6.16' (diff) | |
| parent | Linux 6.17 (diff) | |
| download | kernel-5293dcd7ffda472dbf326c81877bb63d2bfcbd10.tar.gz kernel-5293dcd7ffda472dbf326c81877bb63d2bfcbd10.zip | |
Merge tag 'v6.17'
Linux 6.17
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 4d794964fa0f..89aad5a08928 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -702,18 +702,26 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) int retries; /* Check if the link is up or not */ - for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (dw_pcie_link_up(pci)) break; - msleep(LINK_WAIT_SLEEP_MS); + msleep(PCIE_LINK_WAIT_SLEEP_MS); } - if (retries >= LINK_WAIT_MAX_RETRIES) { + if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) { dev_info(pci->dev, "Phy link never came up\n"); return -ETIMEDOUT; } + /* + * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link + * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms + * after Link training completes before sending a Configuration Request. + */ + if (pci->max_link_speed > 2) + msleep(PCIE_RESET_CONFIG_WAIT_MS); + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); |