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| author | Niklas Cassel <[email protected]> | 2025-05-14 07:43:15 +0000 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2025-05-28 21:47:56 +0000 |
| commit | c8bcb01352a86bc5592403904109c22b66bd916e (patch) | |
| tree | 08767c3e6d40823b65a48ad2a119c540aa60b541 /drivers/pci/controller/dwc/pcie-designware-ep.c | |
| parent | PCI: dwc: ep: Correct PBA offset in .set_msix() callback (diff) | |
| download | kernel-c8bcb01352a86bc5592403904109c22b66bd916e.tar.gz kernel-c8bcb01352a86bc5592403904109c22b66bd916e.zip | |
PCI: cadence-ep: Correct PBA offset in .set_msix() callback
While cdns_pcie_ep_set_msix() writes the Table Size field correctly (N-1),
the calculation of the PBA offset is wrong because it calculates space for
(N-1) entries instead of N.
This results in the following QEMU error when using PCI passthrough on a
device which relies on the PCI endpoint subsystem:
failed to add PCI capability 0x11[0x50]@0xb0: table & pba overlap, or they don't fit in BARs, or don't align
Fix the calculation of PBA offset in the MSI-X capability.
[bhelgaas: more specific subject and commit log]
Fixes: 3ef5d16f50f8 ("PCI: cadence: Add MSI-X support to Endpoint driver")
Signed-off-by: Niklas Cassel <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Wilfred Mallawa <[email protected]>
Reviewed-by: Damien Le Moal <[email protected]>
Cc: [email protected]
Link: https://patch.msgid.link/[email protected]
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware-ep.c')
0 files changed, 0 insertions, 0 deletions