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| author | Selvam Sathappan Periakaruppan <[email protected]> | 2022-06-21 08:54:54 +0000 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2022-07-15 20:30:57 +0000 |
| commit | 0cf7c2efe8ac76bb6b90abc64bcf8df124509d7d (patch) | |
| tree | aeafaa4311fa4b2178fcc5e0158a378f778ab6bf /drivers/pci/controller/dwc/pci-layerscape.c | |
| parent | PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* (diff) | |
| download | kernel-0cf7c2efe8ac76bb6b90abc64bcf8df124509d7d.tar.gz kernel-0cf7c2efe8ac76bb6b90abc64bcf8df124509d7d.zip | |
PCI: qcom: Add IPQ60xx support
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that
platform.
The code is based on downstream[1] Codeaurora kernel v5.4 (branch
win.linuxopenwrt.2.0).
Split out the DBI registers access part from .init into .post_init. DBI
registers are only accessible after phy_power_on().
[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/
Link: https://lore.kernel.org/r/f7f848653c99abbf9a0f877949a44e52329543ae.1655799816.git.baruch@tkos.co.il
Tested-by: Robert Marko <[email protected]>
Signed-off-by: Selvam Sathappan Periakaruppan <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
Acked-by: Stanimir Varbanov <[email protected]>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-layerscape.c')
0 files changed, 0 insertions, 0 deletions