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| author | Niklas Cassel <[email protected]> | 2025-06-25 10:23:51 +0000 |
|---|---|---|
| committer | Manivannan Sadhasivam <[email protected]> | 2025-06-25 13:25:58 +0000 |
| commit | 80dc18a0cba8dea42614f021b20a04354b213d86 (patch) | |
| tree | 1a49da38a7711fa0978975f13712b8b9f47847cd /drivers/pci/controller/dwc/pci-exynos.c | |
| parent | PCI: qcom: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ (diff) | |
| download | kernel-80dc18a0cba8dea42614f021b20a04354b213d86.tar.gz kernel-80dc18a0cba8dea42614f021b20a04354b213d86.zip | |
PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up
As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
training completes before sending a Configuration Request.
Add this delay in dw_pcie_wait_for_link(), after the link is reported as
up. The delay will only be performed in the success case where the link
came up.
DWC glue drivers that have a link up IRQ (drivers that set
use_linkup_irq = true) do not call dw_pcie_wait_for_link(), instead they
perform this delay in their threaded link up IRQ handler.
Signed-off-by: Niklas Cassel <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Damien Le Moal <[email protected]>
Reviewed-by: Wilfred Mallawa <[email protected]>
Link: https://patch.msgid.link/[email protected]
Diffstat (limited to 'drivers/pci/controller/dwc/pci-exynos.c')
0 files changed, 0 insertions, 0 deletions