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| author | Martin Fuzzey <[email protected]> | 2019-10-23 09:44:24 +0000 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2019-10-24 04:44:44 +0000 |
| commit | 76db2d466f6a929a04775f0f87d837e3bcba44e8 (patch) | |
| tree | 1c6e3bfb52d93fc25ea06992920c6ae17330f8e8 /drivers/net/xen-netback/interface.c | |
| parent | net/flow_dissector: switch to siphash (diff) | |
| download | kernel-76db2d466f6a929a04775f0f87d837e3bcba44e8.tar.gz kernel-76db2d466f6a929a04775f0f87d837e3bcba44e8.zip | |
net: phy: smsc: LAN8740: add PHY_RST_AFTER_CLK_EN flag
The LAN8740, like the 8720, also requires a reset after enabling clock.
The datasheet [1] 3.8.5.1 says:
"During a Hardware reset, an external clock must be supplied
to the XTAL1/CLKIN signal."
I have observed this issue on a custom i.MX6 based board with
the LAN8740A.
[1] http://ww1.microchip.com/downloads/en/DeviceDoc/8740a.pdf
Signed-off-by: Martin Fuzzey <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'drivers/net/xen-netback/interface.c')
0 files changed, 0 insertions, 0 deletions