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| author | Jiaxun Yang <[email protected]> | 2024-06-12 08:54:33 +0000 |
|---|---|---|
| committer | Daniel Lezcano <[email protected]> | 2024-07-12 14:07:05 +0000 |
| commit | cc9b2c590ebacf656bb2063c2f6cbfb7ad7081f3 (patch) | |
| tree | 5d94ff5cce909b047978bcd697949ef5cb2e79b5 /drivers/net/ethernet/intel/igc/igc_main.c | |
| parent | clocksource/drivers/sh_cmt: Address race condition for clock events (diff) | |
| download | kernel-cc9b2c590ebacf656bb2063c2f6cbfb7ad7081f3.tar.gz kernel-cc9b2c590ebacf656bb2063c2f6cbfb7ad7081f3.zip | |
clocksource/drivers/mips-gic-timer: Refine rating computation
It is a good clocksource which usually go as fast as CPU core
and have a low access latency, so raise the base of rating
from Good to desired when we know that it has a stable frequency.
Increase frequency addend dividend to 10000000 (10MHz) to
reasonably accommodate multi GHz level clock, also cap rating
within current level.
Signed-off-by: Jiaxun Yang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Daniel Lezcano <[email protected]>
Diffstat (limited to 'drivers/net/ethernet/intel/igc/igc_main.c')
0 files changed, 0 insertions, 0 deletions