diff options
| author | Piotr Raczynski <[email protected]> | 2023-05-15 19:03:17 +0000 |
|---|---|---|
| committer | Tony Nguyen <[email protected]> | 2023-05-16 16:38:38 +0000 |
| commit | 4aad5335969f25c4dc966a15c5497db3718538bb (patch) | |
| tree | d67e1744fdb2291c4ba427ae889b259757773f48 /drivers/net/ethernet/intel/ice/ice_sriov.c | |
| parent | ice: remove redundant SRIOV code (diff) | |
| download | kernel-4aad5335969f25c4dc966a15c5497db3718538bb.tar.gz kernel-4aad5335969f25c4dc966a15c5497db3718538bb.zip | |
ice: add individual interrupt allocation
Currently interrupt allocations, depending on a feature are distributed
in batches. Also, after allocation there is a series of operations that
distributes per irq settings through that batch of interrupts.
Although driver does not yet support dynamic interrupt allocation, keep
allocated interrupts in a pool and add allocation abstraction logic to
make code more flexible. Keep per interrupt information in the
ice_q_vector structure, which yields ice_vsi::base_vector redundant.
Also, as a result there are a few functions that can be removed.
Reviewed-by: Jacob Keller <[email protected]>
Reviewed-by: Michal Swiatkowski <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Tested-by: Pucha Himasekhar Reddy <[email protected]> (A Contingent worker at Intel)
Signed-off-by: Piotr Raczynski <[email protected]>
Signed-off-by: Tony Nguyen <[email protected]>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_sriov.c')
| -rw-r--r-- | drivers/net/ethernet/intel/ice/ice_sriov.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_sriov.c b/drivers/net/ethernet/intel/ice/ice_sriov.c index 65f971b74717..0fc2b26a2fa6 100644 --- a/drivers/net/ethernet/intel/ice/ice_sriov.c +++ b/drivers/net/ethernet/intel/ice/ice_sriov.c @@ -835,7 +835,7 @@ static int ice_ena_vfs(struct ice_pf *pf, u16 num_vfs) int ret; /* Disable global interrupt 0 so we don't try to handle the VFLR. */ - wr32(hw, GLINT_DYN_CTL(pf->oicr_idx), + wr32(hw, GLINT_DYN_CTL(pf->oicr_irq.index), ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S); set_bit(ICE_OICR_INTR_DIS, pf->state); ice_flush(hw); |
