diff options
| author | Sergey Temerkhanov <[email protected]> | 2024-05-28 23:03:53 +0000 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2024-06-01 22:51:50 +0000 |
| commit | 0d80bbe254198ab20982d5c508c55518d32c033b (patch) | |
| tree | 525b1520edad9a3589565b6f6ae4755c567e68d6 /drivers/net/ethernet/intel/ice/ice_ptp_hw.c | |
| parent | ice: Introduce helper to get tmr_cmd_reg values (diff) | |
| download | kernel-0d80bbe254198ab20982d5c508c55518d32c033b.tar.gz kernel-0d80bbe254198ab20982d5c508c55518d32c033b.zip | |
ice: Implement Tx interrupt enablement functions
Introduce functions enabling/disabling Tx TS interrupts
for the E822 and ETH56G PHYs
Signed-off-by: Sergey Temerkhanov <[email protected]>
Reviewed-by: Przemek Kitszel <[email protected]>
Reviewed-by: Arkadiusz Kubalewski <[email protected]>
Signed-off-by: Karol Kolacinski <[email protected]>
Tested-by: Pucha Himasekhar Reddy <[email protected]>
Signed-off-by: Jacob Keller <[email protected]>
Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-3-c082739bb6f6@intel.com
Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_ptp_hw.c')
| -rw-r--r-- | drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 43aa83bc54c2..0a4026c8a3ba 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2720,6 +2720,37 @@ ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) } /** + * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt + * @hw: pointer to the HW struct + * @quad: the timestamp quad + * @ena: enable or disable interrupt + * @threshold: interrupt threshold + * + * Configure TX timestamp interrupt for the specified quad + * + * Return: 0 on success, other error codes when failed to read/write quad + */ + +int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) +{ + int err; + u32 val; + + err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); + if (err) + return err; + + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; + if (ena) { + val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; + val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold); + } + + return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); +} + +/** * ice_ptp_init_phy_e82x - initialize PHY parameters * @ptp: pointer to the PTP HW struct */ |