diff options
| author | Karol Kolacinski <[email protected]> | 2024-08-30 11:07:19 +0000 |
|---|---|---|
| committer | Tony Nguyen <[email protected]> | 2024-10-01 18:11:38 +0000 |
| commit | e4291b64e11889c73fa9c75e74115721758a3fb4 (patch) | |
| tree | 5feafc8950ab2a498411b2ba8df3129fb6bafe9d /drivers/net/ethernet/intel/ice/ice_ptp.h | |
| parent | ice: Add SDPs support for E825C (diff) | |
| download | kernel-e4291b64e11889c73fa9c75e74115721758a3fb4.tar.gz kernel-e4291b64e11889c73fa9c75e74115721758a3fb4.zip | |
ice: Align E810T GPIO to other products
Instead of having separate PTP GPIO implementation for E810T, use
existing one from all other products.
Reviewed-by: Arkadiusz Kubalewski <[email protected]>
Signed-off-by: Karol Kolacinski <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Tested-by: Pucha Himasekhar Reddy <[email protected]> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <[email protected]>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_ptp.h')
| -rw-r--r-- | drivers/net/ethernet/intel/ice/ice_ptp.h | 29 |
1 files changed, 9 insertions, 20 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.h b/drivers/net/ethernet/intel/ice/ice_ptp.h index eccd52108010..4ef6819cfeeb 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp.h @@ -8,24 +8,6 @@ #include <linux/kthread.h> #include "ice_ptp_hw.h" - -enum ice_ptp_pin_e810 { - GPIO_20 = 0, - GPIO_21, - GPIO_22, - GPIO_23, - NUM_PTP_PIN_E810 -}; - -enum ice_ptp_pin_e810t { - GNSS = 0, - SMA1, - UFL1, - SMA2, - UFL2, - NUM_PTP_PINS_E810T -}; - struct ice_perout_channel { bool ena; u32 gpio_pin; @@ -230,6 +212,14 @@ enum ice_ptp_pin { ONE_PPS }; +enum ice_ptp_pin_e810t { + GNSS = 0, + SMA1, + UFL1, + SMA2, + UFL2 +}; + /* Per-channel register definitions */ #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) #define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8)) @@ -241,9 +231,8 @@ enum ice_ptp_pin { #define GLTSYN_EVNT_H_IDX_MAX 3 /* Pin definitions for PTP */ -#define PPS_CLK_GEN_CHAN 3 -#define PPS_PIN_INDEX 5 #define ICE_N_PINS_MAX 6 +#define ICE_SMA_PINS_NUM 4 #define ICE_PIN_DESC_ARR_LEN(_arr) (sizeof(_arr) / \ sizeof(struct ice_ptp_pin_desc)) |