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authorKarol Kolacinski <[email protected]>2025-04-22 16:01:48 +0000
committerTony Nguyen <[email protected]>2025-06-09 16:56:18 +0000
commita33a302b505bfbb9614aa308391a45cf55827496 (patch)
treefd0d1c5c8f3f4e952882f5f841d65773577d3c8e /drivers/net/ethernet/intel/ice/ice_ptp.h
parentice: redesign dpll sma/u.fl pins control (diff)
downloadkernel-a33a302b505bfbb9614aa308391a45cf55827496.tar.gz
kernel-a33a302b505bfbb9614aa308391a45cf55827496.zip
ice: change SMA pins to SDP in PTP API
This change aligns E810 PTP pin control to all other products. Currently, SMA/U.FL port expanders are controlled together with SDP pins connected to 1588 clock. To align this, separate this control by exposing only SDP20..23 pins in PTP API on adapters with DPLL. Clear error for all E810 on absent NVM pin section or other errors to allow proper initialization on SMA E810 with NVM section. Use ARRAY_SIZE for pin array instead of internal definition. Reviewed-by: Milena Olech <[email protected]> Signed-off-by: Karol Kolacinski <[email protected]> Signed-off-by: Arkadiusz Kubalewski <[email protected]> Reviewed-by: Aleksandr Loktionov <[email protected]> Tested-by: Rinitha S <[email protected]> (A Contingent worker at Intel) Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Tony Nguyen <[email protected]>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_ptp.h')
-rw-r--r--drivers/net/ethernet/intel/ice/ice_ptp.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.h b/drivers/net/ethernet/intel/ice/ice_ptp.h
index 3b769a0cad00..c8dac5a5bcd9 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.h
@@ -202,9 +202,6 @@ enum ice_ptp_pin_nvm {
/* Pin definitions for PTP */
#define ICE_N_PINS_MAX 6
-#define ICE_SMA_PINS_NUM 4
-#define ICE_PIN_DESC_ARR_LEN(_arr) (sizeof(_arr) / \
- sizeof(struct ice_ptp_pin_desc))
/**
* struct ice_ptp_pin_desc - hardware pin description data