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authorLucas Stach <[email protected]>2024-07-01 08:53:41 +0000
committerDavid S. Miller <[email protected]>2024-07-03 08:13:38 +0000
commit8d7330b3a9c6db53d4462820df566c0b1e77d831 (patch)
tree6a61c295f0f31f0bc129208a774b3116eddb7aab /drivers/net/dsa/microchip/lan937x_main.c
parentMerge branch 'device-memory-tcp' (diff)
downloadkernel-8d7330b3a9c6db53d4462820df566c0b1e77d831.tar.gz
kernel-8d7330b3a9c6db53d4462820df566c0b1e77d831.zip
net: dsa: microchip: lan9371/2: add 100BaseTX PHY support
On the LAN9371 and LAN9372, the 4th internal PHY is a 100BaseTX PHY instead of a 100BaseT1 PHY. The 100BaseTX PHYs have a different base register offset. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Oleksij Rempel <[email protected]> Acked-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'drivers/net/dsa/microchip/lan937x_main.c')
-rw-r--r--drivers/net/dsa/microchip/lan937x_main.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index b479a628b1ae..eaa862eb6b26 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -55,6 +55,10 @@ static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
u16 temp;
+ if ((dev->info->chip_id == LAN9371_CHIP_ID ||
+ dev->info->chip_id == LAN9372_CHIP_ID) && addr == KSZ_PORT_4)
+ addr_base = REG_PORT_TX_PHY_CTRL_BASE;
+
/* get register address based on the logical port */
temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));