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| author | Jiri Pirko <[email protected]> | 2024-10-30 08:11:57 +0000 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2024-11-03 16:39:07 +0000 |
| commit | e2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff (patch) | |
| tree | 0e2e4e44c21a6e494893e858ad22ebc0b47c0355 /drivers/net/dsa/dsa_loop.c | |
| parent | dpll: add clock quality level attribute and op (diff) | |
| download | kernel-e2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff.tar.gz kernel-e2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff.zip | |
net/mlx5: DPLL, Add clock quality level op implementation
Use MSECQ register to query clock quality from firmware. Implement the
dpll op and fill-up the quality level value properly.
Reviewed-by: Arkadiusz Kubalewski <[email protected]>
Signed-off-by: Jiri Pirko <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'drivers/net/dsa/dsa_loop.c')
0 files changed, 0 insertions, 0 deletions