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| author | Li Ming <[email protected]> | 2025-03-17 07:01:24 +0000 |
|---|---|---|
| committer | Dave Jiang <[email protected]> | 2025-03-20 18:28:45 +0000 |
| commit | aae0594a7053c60b82621136257c8b648c67b512 (patch) | |
| tree | 38e5084de7acb73883ce94893c4b4e0de8f9973d /drivers/net/dsa/dsa_loop.c | |
| parent | Merge branch 'for-6.15/features' into cxl-for-next (diff) | |
| download | kernel-aae0594a7053c60b82621136257c8b648c67b512.tar.gz kernel-aae0594a7053c60b82621136257c8b648c67b512.zip | |
cxl/region: Fix the first aliased address miscalculation
In extended linear cache(ELC) case, cxl_port_get_spa_cache_alias() helps
to get the aliased address of a SPA, it considers the first address in
CXL memory range is "region start + region cache size + 1", but it
should be "region start + region cache size".
So if a SPA is equal to "region start + region cache size", its aliased
address should be "SPA - region cache size".
Signed-off-by: Li Ming <[email protected]>
Reviewed-by: Alison Schofield <[email protected]>
Reviewed-by: Ira Weiny <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Dave Jiang <[email protected]>
Diffstat (limited to 'drivers/net/dsa/dsa_loop.c')
0 files changed, 0 insertions, 0 deletions