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| author | Olga Kitaina <[email protected]> | 2022-06-28 15:48:24 +0000 |
|---|---|---|
| committer | Miquel Raynal <[email protected]> | 2022-06-29 11:38:08 +0000 |
| commit | e16eceea863b417fd328588b1be1a79de0bc937f (patch) | |
| tree | 3f5daf164c4ea3e3dc7e54158159b38a887a4cf5 /drivers/mtd/lpddr/lpddr2_nvm.c | |
| parent | mtd: rawnand: arasan: Update NAND bus clock instead of system clock (diff) | |
| download | kernel-e16eceea863b417fd328588b1be1a79de0bc937f.tar.gz kernel-e16eceea863b417fd328588b1be1a79de0bc937f.zip | |
mtd: rawnand: arasan: Fix clock rate in NV-DDR
According to the Arasan NAND controller spec, the flash clock rate for SDR
must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
which would result in incorrect behavior for NV-DDR modes 0-4.
The appropriate clock rate can be calculated from the NV-DDR timing
parameters as 1/tCK, or for rates measured in picoseconds,
10^12 / nand_nvddr_timings->tCK_min.
Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
CC: [email protected] # 5.8+
Signed-off-by: Olga Kitaina <[email protected]>
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
Diffstat (limited to 'drivers/mtd/lpddr/lpddr2_nvm.c')
0 files changed, 0 insertions, 0 deletions