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| author | Yash Shah <[email protected]> | 2020-01-03 04:13:20 +0000 |
|---|---|---|
| committer | Paul Walmsley <[email protected]> | 2020-01-03 08:56:23 +0000 |
| commit | cfda8617e22a8bf217a613d0b3ba3a38778443ba (patch) | |
| tree | 85fbdb2001a712861d788616d17dc654e28740dd /drivers/iio/trigger/stm32-timer-trigger.c | |
| parent | riscv: gcov: enable gcov for RISC-V (diff) | |
| download | kernel-cfda8617e22a8bf217a613d0b3ba3a38778443ba.tar.gz kernel-cfda8617e22a8bf217a613d0b3ba3a38778443ba.zip | |
riscv: dts: Add DT support for SiFive L2 cache controller
Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file
Signed-off-by: Yash Shah <[email protected]>
Reviewed-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
Diffstat (limited to 'drivers/iio/trigger/stm32-timer-trigger.c')
0 files changed, 0 insertions, 0 deletions