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| author | Fabrice Gasnier <[email protected]> | 2017-09-18 10:05:30 +0000 |
|---|---|---|
| committer | Jonathan Cameron <[email protected]> | 2017-09-24 12:08:48 +0000 |
| commit | 0a56eabc4e3f730782e4a9f3af4f60aa03a8a849 (patch) | |
| tree | 4777099a1cb23ba0532eeea75f3561dcf260aed8 /drivers/iio/trigger/stm32-timer-trigger.c | |
| parent | iio: adc: twl4030: Return an error if we can not enable the vusb3v1 regulator... (diff) | |
| download | kernel-0a56eabc4e3f730782e4a9f3af4f60aa03a8a849.tar.gz kernel-0a56eabc4e3f730782e4a9f3af4f60aa03a8a849.zip | |
iio: trigger: stm32-timer: preset shouldn't be buffered
Currently, setting preset value (ARR) will update directly 'Auto reload
value' only on 1st write access. But then, ARPE is set. This makes
ARR a shadow register. Preset value should be updated upon each
write request: ensure ARPE is 0. This fixes successive writes to
preset attribute.
Fixes: 4adec7da0536 ("iio: stm32 trigger: Add quadrature encoder device")
Signed-off-by: Fabrice Gasnier <[email protected]>
Cc: <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Diffstat (limited to 'drivers/iio/trigger/stm32-timer-trigger.c')
| -rw-r--r-- | drivers/iio/trigger/stm32-timer-trigger.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c index a9bc5b603b86..4cec28af3ecf 100644 --- a/drivers/iio/trigger/stm32-timer-trigger.c +++ b/drivers/iio/trigger/stm32-timer-trigger.c @@ -681,8 +681,9 @@ static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, if (ret) return ret; + /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); regmap_write(priv->regmap, TIM_ARR, preset); - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); return len; } |