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authorIngo Molnar <[email protected]>2025-04-09 20:28:55 +0000
committerIngo Molnar <[email protected]>2025-04-10 09:58:33 +0000
commit78255eb23973323633432d9ec40b65c15e41888a (patch)
treec5e831fc40abe86e249a66e81dda9b883a1536b6 /drivers/idle/intel_idle.c
parentx86/msr: Rename 'rdmsrl()' to 'rdmsrq()' (diff)
downloadkernel-78255eb23973323633432d9ec40b65c15e41888a.tar.gz
kernel-78255eb23973323633432d9ec40b65c15e41888a.zip
x86/msr: Rename 'wrmsrl()' to 'wrmsrq()'
Suggested-by: "H. Peter Anvin" <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Acked-by: Peter Zijlstra (Intel) <[email protected]> Cc: Juergen Gross <[email protected]> Cc: Dave Hansen <[email protected]> Cc: Xin Li <[email protected]> Cc: Linus Torvalds <[email protected]>
Diffstat (limited to 'drivers/idle/intel_idle.c')
-rw-r--r--drivers/idle/intel_idle.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 6e4b5b33ba81..517b28a85560 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -2082,8 +2082,8 @@ static void __init spr_idle_state_table_update(void)
*/
static void __init byt_cht_auto_demotion_disable(void)
{
- wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
- wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
+ wrmsrq(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
+ wrmsrq(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
}
static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
@@ -2243,7 +2243,7 @@ static void auto_demotion_disable(void)
rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
msr_bits &= ~auto_demotion_disable_flags;
- wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
+ wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
}
static void c1e_promotion_enable(void)
@@ -2252,7 +2252,7 @@ static void c1e_promotion_enable(void)
rdmsrq(MSR_IA32_POWER_CTL, msr_bits);
msr_bits |= 0x2;
- wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
+ wrmsrq(MSR_IA32_POWER_CTL, msr_bits);
}
static void c1e_promotion_disable(void)
@@ -2261,7 +2261,7 @@ static void c1e_promotion_disable(void)
rdmsrq(MSR_IA32_POWER_CTL, msr_bits);
msr_bits &= ~0x2;
- wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
+ wrmsrq(MSR_IA32_POWER_CTL, msr_bits);
}
/**