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authorAlistair Popple <[email protected]>2021-07-01 01:54:35 +0000
committerLinus Torvalds <[email protected]>2021-07-01 18:06:04 +0000
commit8f187163eb890d6d2a53f7efea2b6963fe9526e2 (patch)
tree7f7483626a28203dc07713a313bd62a4a002abe3 /drivers/hwtracing/coresight/coresight-cpu-debug.c
parentnouveau/svm: refactor nouveau_range_fault (diff)
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nouveau/svm: implement atomic SVM access
Some NVIDIA GPUs do not support direct atomic access to system memory via PCIe. Instead this must be emulated by granting the GPU exclusive access to the memory. This is achieved by replacing CPU page table entries with special swap entries that fault on userspace access. The driver then grants the GPU permission to update the page undergoing atomic access via the GPU page tables. When CPU access to the page is required a CPU fault is raised which calls into the device driver via MMU notifiers to revoke the atomic access. The original page table entries are then restored allowing CPU access to proceed. Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Alistair Popple <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Cc: Christoph Hellwig <[email protected]> Cc: Hugh Dickins <[email protected]> Cc: Jason Gunthorpe <[email protected]> Cc: John Hubbard <[email protected]> Cc: "Matthew Wilcox (Oracle)" <[email protected]> Cc: Peter Xu <[email protected]> Cc: Ralph Campbell <[email protected]> Cc: Shakeel Butt <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
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